With rapid progresses in display technologies, high-definition display apparatus has become the mainstream in the market, and high-speed digital transmission interfaces, for example, High Definition Multimedia Interface (HDMI), are established accordingly. High-speed digital transmission interfaces can effectively reduce the demand of memory in high-definition display apparatuses without strict requirements in processing speed of display chips. For improving the display processing efficiency, the processing speed of display chips can be achieved by using novel semiconductor technologies. However, the bandwidth of the memories used in the display chips is still the technical bottleneck. In a multi-chip system, the power consumption of accessing DRAM in a videophone system occupies 60% of the total power consumption. Thereby, embedded-DRAM or embedded-SRAM technologies are used to reduce the power consumption of accessing frame buffers. Nevertheless, the production yield of chips affects severely the capacity of built-in storage. If the built-in storage capacity is increased for high-end display specifications, the problem of production yield will occur, which will result in an increase in overall cost. Besides, the problems of power consumption and bandwidth described above still cannot be solved.
For solving the problems described above, embedded encoding/decoding units are set in modern video apparatus for reducing the requirement in memory bandwidth and the input/output power of frame buffers. FIG. 1 shows a block diagram of an image display chip according to the prior art. As shown in the figure, the image display chip 10 comprises a first encoding/decoding unit 12, a second encoding/decoding unit 14, a third encoding/decoding unit 16, a fourth encoding/decoding unit 18, an HDMI unit 20, an image hardware processing unit 22, a sequential progressive scan unit 24, and a timing controller for liquid crystal display (LCD) 26. The first encoding/decoding unit 12, the second encoding/decoding unit 14, the third encoding/decoding unit 16, and the fourth encoding/decoding unit 18 are embedded encoding/decoding units. The first encoding/decoding unit 12 is coupled to the HDMI unit 20; the second encoding/decoding unit 14 is coupled to the image hardware processing unit 22; the third encoding/decoding unit 16 is coupled to the sequential progressive scan unit 24; and the fourth encoding/decoding unit 18 is coupled to the timing controller for LCD 26. In addition, the first encoding/decoding unit 12, the second encoding/decoding unit 14, the third encoding/decoding unit 16, and the fourth encoding/decoding unit 18 are coupled in parallel with a system bus 102, which is further coupled to an external memory 104. The HDMI unit 20 is further coupled to a transmission line 11. The timing controller for LCD 26 is further coupled to an LCD 30.
The image display chip 10 according to the prior art receives a video signal transmitted by the transmission line 11 via the HDMI unit 20, and the video signal is compressed by the first encoding/decoding unit 12 and is registered in the external memory 104. Alternatively, an image signal is read by the image hardware processing unit 22, and the image signal is compressed by the second encoding/decoding unit 14 and is registered in the external memory 104. Or, a scan signal is given by scanning a frame by the sequential progressive scan unit 24, and the scan signal is encoded by the third encoding/decoding unit 16 and is registered in the external memory 104. Then, the video signal, the image signal, or the scan signal registered in the external memory 104 is read by the fourth encoding/decoding unit 18 via the system bus 102, and is transmitted to the timing controller for LCD 26. The timing controller for LCD 26 is driven to control the LCD for displaying according to the video signal, the image signal, or the scan signal. In the image display chip 10 according to the prior art, the transmission rate of the embedded encoding/decoding unit has to be as high as possible for display applications, especially for displaying high-definition images. The image display chip 10 according to the prior art also should be compatible to other displaying modes. The gate count of the embedded encoding/decoding unit is usually simplified for reducing the cost and hence reducing the price of the image display chip, so that the price is acceptable to the public. Besides, the encoding efficiency of a general embedded encoding/decoding unit can provide a preferable compression ratio. Thereby, the embedded encoding/decoding unit includes the functions of high transmission rate, compact gate count, and preferable encoding efficiency.
Many complicated lossless compression method, such as JPEG-LS and CALIC, adopt numerous sophisticated algorithms for improving encoding efficiency. However, the complexity and dependency of data series of those algorithms limit the possibility of development in embedded encoding/decoding units. In a complex algorithm, fast, efficient, and a lossless image compression system is suitable for the algorithm of embedded encoding/decoding units with preferable encoding efficiency. Nevertheless, the problem caused by data dependency still exists. For example, the amount of data for encoding/decoding is increased when the next pixel is processed according to the encoding/decoding parameters produced during the encoding/decoding process for the previous pixels. Besides, the problem of data dependency limits the compatibility when image processing is applied to high transmission rate.
Accordingly, the present invention provides an apparatus for image processing for providing preferable encoding efficiency and transmission efficiency to solve the problems described above.